M16CSLASH62M datasheet(250/615 Pages) RENESAS

250 / 615 page

CPU Rewrite Mode (Flash Memory Version)

Mitsubishi microcomputers

M16C / 62A Group

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

1-231

Each bit of

SRD

SR4 (bit4)

SR5 (bit5)

SR7 (bit7)

SR6 (bit6)

Status name

Definition

SR1 (bit1)

SR2 (bit2)

SR3 (bit3)

SR0 (bit0)

"1"

"0"

Program status

Erase status

Write state machine (WSM) status

Reserved

Block status after program

Reserved

Ready

Busy

Terminated in error

Terminated normally

Program status (SR4)

The program status informs the operating status of auto write operation to the CPU. When a write

error occurs, it is set to “1”.

The program status is reset to “0” when cleared.

When an erase command is in error (which occurs if the command entered after the block erase

command (2016) is not the confirmation command (D016), both the program status and erase status

(SR5) are set to “1”.

When the program status or erase status = “1”, only the following flash commands will be accepted:

Read Array, Read Status Register, and Clear Status Register.

Also, in one of the following cases, both SR4 and SR5 are set to “1” (command sequence error):

(1) When the valid command is not entered correctly

(2) When the data entered in the second bus cycle of lock bit program (7716/D016), block erase

(2016/D016), or erase all unlock blocks (A716/D016) is not the D016 or FF16. However, if FF16 is

entered, read array is assumed and the command that has been set up in the first bus cycle is

canceled.

Block status after program (SR3)

If excessive data is written (phenomenon whereby the memory cell becomes depressed which results

in data not being read correctly), “1” is set for the program status after-program at the end of the page

write operation. In other words, when writing ends successfully, “8016” is output; when writing fails,

“9016” is output; and when excessive data is written, “8816” is output.

Table 1.26.2. Definition of each bit in status register

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