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M16C/62 데이터시트(PDF) 340 Page - Renesas Technology Corp

부품명 M16C/62
상세설명  16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY
PDF  621 Pages
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제조업체  RENESAS [Renesas Technology Corp]
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M16C/62 데이터시트(HTML) 340 Page - Renesas Technology Corp

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Timer B
Mitsubishi microcomputers
M16C / 62 Group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
325
(1) The timer Bi interrupt request bit goes to “1” when an effective edge of a measurement pulse
is input or timer Bi is overflowed. The factor of interrupt request can be determined by use of
the timer Bi overflow flag within the interrupt routine.
(2) If the timer overflow occurs simultaneously with the input of a measurement pulse, and if the
interrupt factor cannot be determined from the timer Bi overflow flag, connect the timers and
count the number of overflows.
(3) When reset, the timer Bi overflow flag goes to “1”. This flag can be set to “0” by writing to the
timer Bi mode register when the count start flag is “1”.
(4) Use the timer Bi interrupt request bit to detect only overflows. Use the timer Bi overflow flag
only to determine the interrupt factor within the interrupt routine.
(5) When the first effective edge is input after a count is started, an indeterminate value is trans-
ferred to the reload register. At this time, timer Bi interrupt request is not generated.
(6) The value of the counter is indeterminate at the beginning of a count. Therefore the timer Bi
overflow flag may go to “1” immediately after a count is started.
(7) If changing the measurement mode select bit is set after a count is started, the timer Bi
interrupt request bit goes to “1”.
(8) If the input signal to the TBiIN pin is affected by noise, precise measurement may not be
performed in some cases. It is recommended to see that measurements fall within a specific
range by use of software.
(9) For pulse width measurement, pulse widths are successively measured. Use software to
check whether the measurement result is an “H” level width or an “L” level width.
2.3.7 Precautions for Timer B (pulse period/pulse width measurement mode)



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