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M38043FDHKP 데이터시트(PDF) 186 Page - Renesas Technology Corp |
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M38043FDHKP 데이터시트(HTML) 186 Page - Renesas Technology Corp |
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186 / 387 page ![]() 2-62 APPLICATION 2.4 Serial interface Rev.1.00 Jan 14, 2005 REJ09B0212-0100Z 3804 Group (Spec.H) Fig. 2.4.21 Registers setting relevant to transmitting side Serial I/O1 status register (Address : 001916) SIO1STS Transmit buffer empty flag • Confirm that the data has been transferred from Transmit buffer register to Transmit shift register. • When this flag is “1”, it is possible to write the next transmission data in to Transmit buffer register. Transmitting side Transmit shift register shift completion flag Confirm completion of transmitting 1-byte data with this flag. “1” : Transmit shift completed b7 b0 Interrupt edge selection register (Address : 003A16) INTEDGE INT1 falling edge active b7 b0 Baud rate generator 1 (Address : 001C16) BRG1 Set “division ratio – 1” 8 – 1 b7 b0 Serial I/O1 control register (Address : 001A16) SIO1CON BRG count source : f(XIN) Serial I/O1 synchronous clock : BRG/4 Transmit enabled Receive disabled Clock synchronous serial I/O Serial I/O1 enabled b7 b0 0 0 0 11 1 0 Port P4 direction register (Address : 000916) P4D Port P42/INT1: Input mode b7 b0 0 |
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