M38043FDHKP datasheet(285/387 Pages) RENESAS

285 / 387 page

2-161

APPLICATION

2.13 Flash memory mode

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

Also, execute the following processing before the CPU reprogramming mode is selected so that

interrupts will not occur during the CPU reprogramming mode.

• Set the interrupt disable flag (I) to “1”

When the watchdog timer has already started, write to the watchdog timer control register (address

001E16) periodically during the CPU reprogramming mode in order not to generate the reset by the

underflow of the watchdog timer H.

During the program or erase execution, watchdog timer is automatically cleared. Accordingly, the

inernal reset by underflow does not occur.

When the interrupt request or reset occurs in the CPU reprogramming mode, the microcomputer

enters the following state;

• Interrupt occurs

This may cause a program runaway because the read from the flash memory which has the interrupt

vector area cannot be performed.

• Underflow of watchdog timer H, reset

This may cause a microcomputer reset; the built-in flash memory control circuit and the flash memory

control register are reset. When reset state is released with CNVss = “H” and P45/TxD1 = “H”, CPU

starts in the boot mode.

Also, when the above interrupt and reset occur during program/erase, error data may still exist after

reset release because the reprogramming of the flash memory is not completed, so that reprogramming

of the flash memory in the parallel I/O mode or serial I/O mode is required.

M38043FDHKP 데이터시트(PDF) 285 Page - Renesas Technology Corp