M38046FDHKP datasheet(211/387 Pages) RENESAS

211 / 387 page

2-87

APPLICATION

2.5 Multi-master I2C-BUS interface

Rev.1.00 Jan 14, 2005

REJ09B0212-0100Z

3804 Group (Spec.H)

Fig. 2.5.5 Structure of I2C status register

I2C status register

b7 b6 b5 b4 b3 b2 b1 b0

I2C status register

(S1: address 001316)

0: Last bit = 0

1: Last bit = 1 (Note 1)

Name

Functions

At reset R W

0: No general call detected

1: General call detected

(Notes 1, 2)

0: Address disagreement

1: Address agreement

(Notes 1, 2)

Undefined

Last receive bit

(LRB)

General call

detection flag

(AD0)

SCL pin low hold

bit (PIN)

Arbitration lost

detection flag (AL)

Slave address

comparison flag

(AAS)

Bus busy flag (BB)

Communication

mode specification

bits (TRX, MST)

0: SCL pin low hold (Note 3)

1: SCL pin low release

0: Bus free

1: Bus busy

b7 b6

0 0: Slave receive mode

0 1: Slave transmit mode

1 0: Master receive mode

1 1: Master transmit mode

Notes 1: These flags and bits are exclusive to input. When writing to

these bits, write 0 to these bits.

2: These bits can be detected only when the data format

selection bit (ALS) of I2C control register is set to 0 .

3: This bit can be set to 1 by program, but cannot be cleared

to 0 .

4: All bits are changed by hardware. Do not use the read-

modify-write instructions (SEB, CLB).

0: Not detected

1: Detected (Note 1)

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