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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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M38048FDHKP 데이터시트(PDF) 304 Page - Renesas Technology Corp |
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M38048FDHKP 데이터시트(HTML) 304 Page - Renesas Technology Corp |
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304 / 387 page  3-14 REJ09B0212-0100Z Rev.1.00 Jan 14, 2005 3804 Group (Spec.H) APPENDIX 3.1 Electrical characteristics Table 3.1.14 Multi-master I2C-BUS bus line characteristics Fig. 3.1.4 Timing diagram of multi-master I2C-BUS tBUF tHD:STA tHD:DAT tLOW tR tF tHIGH tsu:DAT tsu:STA tHD:STA tsu:STO SCL P S Sr P SDA S : START condition Sr: RESTART condition P : STOP condition Symbol Parameter Unit Bus free time Hold time for START condition Hold time for SCL clock = “0” Rising time of both SCL and SDA signals Data hold time Hold time for SCL clock = “1” Falling time of both SCL and SDA signals Data setup time Setup time for repeated START condition Setup time for STOP condition tBUF tHD;STA tLOW tR tHD;DAT tHIGH tF tSU;DAT tSU;STA tSU;STO Min. Max. Min. Max. µs µs µs ns µs µs ns ns µs µs Standard clock mode High-speed clock mode Note: Cb = total capacitance of 1 bus line 4.7 4.0 4.7 0 4.0 250 4.7 4.0 1000 300 1.3 0.6 1.3 20+0.1Cb 0 0.6 20+0.1Cb 100 0.6 0.6 300 0.9 300 3.1.8 Multi-master I2C-BUS bus line characteristics |
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