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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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M38049FDHKP 데이터시트(PDF) 233 Page - Renesas Technology Corp |
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M38049FDHKP 데이터시트(HTML) 233 Page - Renesas Technology Corp |
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233 / 387 page  2-109 APPLICATION 2.5 Multi-master I2C-BUS interface Rev.1.00 Jan 14, 2004 REJ09B0212-0100Z 3804 Group (Spec.H) ➁ Reception of command Confirm correct completion of the command reception in the interrupt after receiving the command. After confirming correct command from the host, write dummy data to the I2C data shift register to wait for reception of the next slave address. Fig. 2.5.30 Reception process of command End S0 (address 001116) ← 111111112 Error end Receive data buffer ← S0 (address 001116) S2 (address 001516) ← 100001012 Judgment of receive command PIN (address 001316), bit 4 ? 1 (STOP condition) 0 (command received) 2 S1 (address 001316) ← 000100002 • Judgment of bus hold • “ACK clock is used” select and “ACK is returned” set • Slave receive mode set • Dummy data write to I2C data shift register • Receive data read and save |
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