AT89C5122DS-RDRUM datasheet(116/208 Pages) ATMEL

116 / 208 page

116

AT83R5122, AT8xC5122/23

4202F–SCR–07/2008

Reset Value = 0000 0000b

Table 65.

USB Global Interrupt Register - USBINT (S:BDh)

765

43210

WUPCPU

EORINT

SOFINT

SPINT

Bit Number

Bit

Mnemonic Description

7 - 6

Reserved

The value read from these bits is always 0. Do not change these bits.

WUPCPU

Wake-up CPU Interrupt

This bit is set by hardware when the USB controller is in SUSPEND state and is

re-activated by a non-idle signal FROM USB line (not by an upstream resume).

This triggers a USB interrupt when EWUPCPU is set in the Table on page 117.

When receiving this interrupt, user has to enable all USB clock inputs.

This bit should be cleared by software (USB clocks must be enabled before).

4EORINT

End of Reset Interrupt

This bit is set by hardware when End of Reset has been detected by the USB

controller. This triggers a USB interrupt when EEORINT is set in the Table on

page 117.

This bit should be cleared by software.

3SOFINT

Start Of Frame Interrupt

This bit is set by hardware when an USB Start Of Frame PID (SOF) has been

detected. This triggers a USB interrupt when ESOFINT is set in the Table on

page 117.

This bit should be cleared by software.

2-1

Reserved

The value read from these bits is always 0. Do not change these bits.

0SPINT

Suspend Interrupt

This bit is set by hardware when a USB Suspend (Idle bus for three frame

periods: a J state for 3 ms) is detected. This triggers a USB interrupt when

ESPINT is set in USBIEN register (Table 66 on page 117).

This bit must be cleared by software before powering the microcontroller down

as it disables the USB pads to reduce the power consumption.

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