ATmega324P datasheet(141/377 Pages) ATMEL

141 / 377 page

141

7674F–AVR–09/09

ATmega164P/324P/644P

15.4

Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

15-2 shows a block diagram of the counter and its surrounding environment.

Figure 15-2. Counter Unit Block Diagram

Signal description (internal signals):

count

Increment or decrement TCNT2 by 1.

direction

Selects between increment and decrement.

clear

Clear TCNT2 (set all bits to zero).

clk

Timer/Counter clock, referred to as clk

T2 in the following.

top

Signalizes that TCNT2 has reached maximum value.

bottom

Signalizes that TCNT2 has reached minimum value (zero).

Depending on the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clk

T2). clkT2 can be generated from an external or internal clock source,

selected by the Clock Select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the

timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of

whether clk

T2 is present or not. A CPU write overrides (has priority over) all counter clear or

count operations.

The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in

the Timer/Counter Control Register (TCCR2A) and the WGM22 located in the Timer/Counter

Control Register B (TCCR2B). There are close connections between how the counter behaves

(counts) and how waveforms are generated on the Output Compare outputs OC2A and OC2B.

For more details about advanced counting sequences and waveform generation, see “Modes of

Operation” on page 145.

The Timer/Counter Overflow Flag (TOV2) is set according to the mode of operation selected by

the WGM22:0 bits. TOV2 can be used for generating a CPU interrupt.

DATA BUS

TCNTn

Control Logic

count

TOVn

(Int.Req.)

top

bottom

direction

clear

TOSC1

T/C

Oscillator

TOSC2

Prescaler

clk

I/O

clk

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