ATmega328P datasheet(177/448 Pages) ATMEL

177 / 448 page

177

8161D–AVR–10/09

ATmega48PA/88PA/168PA/328P

Figure 19-1. USART Block Diagram

(1)

Note:

1. Refer to Figure 1-1 on page 2 and Table 13-9 on page 88 for USART0 pin placement.

19.3

Clock Generation

The Clock Generation logic generates the base clock for the Transmitter and Receiver. The

USART supports four modes of clock operation: Normal asynchronous, Double Speed asyn-

chronous, Master synchronous and Slave synchronous mode. The UMSELn bit in USART

Control and Status Register C (UCSRnC) selects between asynchronous and synchronous

operation. Double Speed (asynchronous mode only) is controlled by the U2Xn found in the

UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register

for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or

external (Slave mode). The XCKn pin is only active when using synchronous mode.

PARITY

GENERATOR

UBRRn [H:L]

UDRn(Transmit)

UCSRnA

UCSRnB

UCSRnC

BAUD RATE GENERATOR

TRANSMIT SHIFT REGISTER

RECEIVE SHIFT REGISTER

RxDn

TxDn

CONTROL

UDRn(Receive)

CONTROL

XCKn

DATA

RECOVERY

CLOCK

RECOVERY

CONTROL

PARITY

CHECKER

OSC

SYNC LOGIC

Clock Generator

Transmitter

Receiver

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