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HT68F20 데이터시트(PDF) 104 Page - Holtek Semiconductor Inc

부품명 HT68F20
상세설명  Enhanced I/O Flash Type MCU 8-Bit MCU with EEPROM
PDF  210 Pages
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제조업체  HOLTEK [Holtek Semiconductor Inc]
홈페이지  http://www.holtek.com
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HT68F20 데이터시트(HTML) 104 Page - Holtek Semiconductor Inc

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HT68F20/HT68F30/HT68F40/HT68F50/HT68F60
Rev.1.00
104
November 3, 2009
Single Pulse Mode
To select this mode, bits TnM1 and TnM0 in the TMnC1
register should be set to 10 respectively and also the
TnIO1 and TnIO0 bits should be set to 11 respectively.
The Single Pulse Output Mode, as the name suggests,
will generate a single shot pulse on the TM output pin.
The trigger for the pulse output leading edge is a low to
high transition of the TnON bit, which can be imple-
mented using the application program. However in the
Single Pulse Mode, the TnON bit can also be made to
automatically change from low to high using the external
TCKn pin, which will in turn initiate the Single Pulse out-
put. When the TnON bit transitions to a high level, the
counter will start running and the pulse leading edge will
be generated. The TnON bit should remain high when
the pulse is in its active state. The generated pulse trail-
ing edge will be generated when the TnON bit is cleared
to zero, which can be implemented using the application
program or when a compare match occurs from Com-
parator A.
L e a d i n g E d g e
T n O N b i t
0 ® 1
S / W C o m m a n d
S E T " T n O N "
o r
T C K n P i n T r a n s i t i o n
T n O N b i t
1 ® 0
S / W C o m m a n d
C L R " T n O N "
o r
C C R A M a t c h C o m p a r e
P u l s e W i d t h = C C R A V a l u e
T r a i l i n g E d g e
T M n O u t p u t P i n
Single Pulse Generation
CCRA
CCRP
Counter
Value
Counter Stopped
by CCRA
CCRP Int.
Flag TnPF
CCRA Int.
Flag TnAF
TM Pin
TnOC = 1
TnON bit
Pulse Width
set by CCRA
TnIO1, TnIO 0 = 11 Single Pulse Output
TnIO 1, TnIO0 = 00
Output Inact ive
TnIO1, TnI O0 = 11
No CCRP
Interrupt
generated
Here TnIO 1, TnIO0 = 00
Output Forced to Inactive
level but counter keeps
running internally
TnIO 1, TnIO0 = 11
Resume Single Pulse O utput
Counter Stops
by soft ware
Count er reset
when TnON
returns high
Time
TnPOL bit
Out put Inverts
When TnPOL = 1
TM Pin
TnOC = 0
TnPAU bit
Resume
Pause
Sof tware
Trigger
TCKn pin
Cleared by
CCRA match
TCKn pin
Trigger
Auto. s et
by TCKn pin
Soft ware
Clear
Software
Trigger
Software
Trigger
TnM1, TnM0 = 10; TnIO1, TnIO0 = 11
Single Pulse Mode
Note:
1. Counter stopped by CCRA match
2. CCRP is not used
3. Pulse triggered by TCKn pin or setting TnON bit high
4. TCKn pin active edge will auto set TnON bit



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