PIC12F615-ESLASHMS datasheet(119/212 Pages) MICROCHIP

119 / 212 page

 2010 Microchip Technology Inc.

DS41302D-page 119

PIC12F609/615/617/12HV609/615

12.4.2

TIMER0 INTERRUPT

An overflow (FFh

 00h) in the TMR0 register will set

the T0IF bit of the INTCON register. The interrupt can

be enabled/disabled by setting/clearing T0IE bit of the

INTCON register. See Section 6.0 “Timer0 Module”

for operation of the Timer0 module.

12.4.3

GPIO INTERRUPT-ON-CHANGE

An input change on GPIO sets the GPIF bit of the

INTCON register. The interrupt can be enabled/

disabled by setting/clearing the GPIE bit of the

INTCON

Plus,

individual

pins

can

configured through the IOC register.

FIGURE 12-7:

INTERRUPT LOGIC

Note:

If a change on the I/O pin should occur

when

any

GPIO

operation

being

executed, then the GPIF interrupt flag may

not get set.

TMR1IF

TMR1IE

CMIF

CMIE

T0IF

T0IE

INTF

INTE

GPIF

GPIE

GIE

PEIE

Wake-up (If in Sleep mode)(1)

Interrupt to CPU

ADIF

ADIE

IOC-GP0

IOC0

IOC-GP1

IOC1

IOC-GP2

IOC2

IOC-GP3

IOC3

IOC-GP4

IOC4

IOC-GP5

IOC5

TMR2IF

TMR2IE

CCP1IF

CCP1IE

Note

Some peripherals depend upon the system clock for

operation. Since the system clock is suspended during Sleep, only

those peripherals which do not depend upon the system clock will wake

the part from Sleep. See Section 12.7.1 “Wake-up from Sleep”.

(615/617

(615/617 only)

only)

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