TMP320C6720RFP300 datasheet(104/118 Pages) TI

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4.18 Phase-Locked Loop (PLL)

4.18.1 PLL Device-Specific Information

PLLEN

(PLL_CSR[0])

Divider

(/1 to /32)

PLLREF

PLL

x4 to x25

PLLOUT

Divider

(/1 to /32)

SYSCLK1

CPU and Memory

Divider

(/1 to /32)

SYSCLK2

Peripherals and dMAX

Divider

(/1 to /32)

SYSCLK3

EMIF

AUXCLK

McASP0,1,2

Clock

Input

from

CLKIN or

OSCIN

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720

Floating-Point Digital Signal Processors

SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008

www.ti.com

The C672x DSP generates the high-frequency internal clocks it requires through an on-chip PLL.

The input to the PLL is either from the on-chip oscillator (OSCIN pin) or from an external clock on the

CLKIN pin. The PLL outputs four clocks that have programmable divider options. Figure 4-43 illustrates

the PLL Topology.

The PLL is disabled by default after a device reset. It must be configured by software according to the

allowable operating conditions listed in Table 4-42 before enabling the DSP to run from the PLL by setting

PLLEN = 1.

Figure 4-43. PLL Topology

Peripheral and Electrical Specifications

104

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