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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LH79524 데이터시트(PDF) 31 Page - NXP Semiconductors |
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LH79524 데이터시트(HTML) 31 Page - NXP Semiconductors |
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31 / 64 page  System-on-Chip LH79524/LH79525 Preliminary data sheet Rev. 01 — 16 July 2007 31 NXP Semiconductors nWE Output 30 pF tOVSDW tSDCLK/2 + 4.5 ns SDWE Write Enable Valid tOHSDW tSDCLK/2 – 4.0 ns SDWE Write Enable Hold SDCKE Output 30 pF tOVC0 tSDCLK/2 + 4.5 ns SDCKE Clock Enable Valid tOHC0 tSDCLK/2 – 4.0 ns SDCKE Clock Enable Hold DQM[3:0] Output 30 pF tOVDQ tSDCLK/2 + 5.0 ns DQM Data Mask Valid tOHDQ tSDCLK/2 – 4.0 ns DQM Data Mask Hold nSDCS[1:0] Output 30 pF tOVSC tSDCLK/2 + 4.5 ns SDCS Data Mask Valid tOHSC tSDCLK/2 – 4.0 ns SDCS Data Mask Hold SDCLK Output 30 pF tSDCLK 19.37 ns SDRAM Clock Period SYNCHRONOUS SERIAL PORT (SSP) SSPFRM Output 50 pF tOVSSPFRM 14 ns tOVSSPFRM Output Valid, Referenced to SSPCLK SSPTX Output 50 pF tOVSSPTX 14 ns SSP Transmit Valid SSPRX Input tISSPRX 20 ns SSP Receive Setup ETHERNET MAC CONTROLLER (EMC) ETHERTXER Output 50 pF tOVTXER 25 ns Transmit Data Valid after ETHERTXCLK tOHTXER ETHERTXCLK/2 + 2.0 ns Transmit Data Hold after ETHERTXCLK ETHERTX[3:0] Output 50 pF tOVTXD 25 ns Transmit Data Valid after ETHERTXCLK tOHTXD ETHERTXCLK/2 + 2.0 ns Transmit Data Hold after ETHERTXCLK ETHERTXEN Output 50 pF tOVTXEN 25 ns Transmit Data Valid after ETHERTXCLK tOHTXEN ETHERTXCLK/2 + 2.0 ns Transmit Data Hold after ETHERTXCLK ETHERRXDV Input tISRXDV 10 ns Receive Data Setup prior to ETHERRXCLK tIHRXDV 10 ns Receive Data Hold prior to ETHERRXCLK ETHERRX[3:0] Input tISRXD 10 ns Receive Data Setup prior to ETHERRXCLK tIHRXD 10 ns Receive Data Hold prior to ETHERRXCLK Table 14. AC Signal Characteristics (Cont’d) SIGNAL TYPE LOAD SYMBOL MIN. MAX. DESCRIPTION |
유사한 부품 번호 - LH79524 |
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유사한 설명 - LH79524 |
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