PIC18F4580-ESLASHML datasheet(218/490 Pages) MICROCHIP

부품명	PIC18F4580-E/ML

상세설명	28/40/44-Pin Enhanced Flash Microcontrollers with ECAN Technology, 10-Bit A/D and nanoWatt Technology

PDF	490 Pages

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218 / 490 page

PIC18F2480/2580/4480/4580

DS39637D-page 218

18.4.7.1

Clock Arbitration

Clock arbitration occurs when the master, during any

receive, transmit or Repeated Start/Stop condition,

deasserts the SCL pin (SCL allowed to float high).

When the SCL pin is allowed to float high, the Baud

Rate Generator (BRG) is suspended from counting

until the SCL pin is actually sampled high. When the

SCL pin is sampled high, the Baud Rate Generator is

reloaded with the contents of SSPADD<6:0> and

begins counting. This ensures that the SCL high time

will always be at least one BRG rollover count in the

event that the clock is held low by an external device

(Figure 18-18).

FIGURE 18-18:

BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

SDA

SCL

SCL deasserted but slave holds

DX – 1

BRG

SCL is sampled high, reload takes

place and BRG starts its count

03h

02h

01h

00h (hold off)

03h

02h

Reload

BRG

Value

SCL low (clock arbitration)

SCL allowed to transition high

BRG decrements on

Q2 and Q4 cycles

PIC18F4580-E/ML 데이터시트(PDF) 218 Page - Microchip Technology