| 전자부품 데이터시트 검색엔진 |
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PIC18F4580-E/ML 데이터시트(PDF) 446 Page - Microchip Technology |
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PIC18F4580-E/ML 데이터시트(HTML) 446 Page - Microchip Technology |
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446 / 490 page ![]() PIC18F2480/2580/4480/4580 DS39637D-page 446 © 2009 Microchip Technology Inc. FIGURE 28-11: PARALLEL SLAVE PORT TIMING (PIC18F4480/4580) TABLE 28-13: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4480/4580) Param. No. Symbol Characteristic Min Max Units Conditions 62 TDTV2WRH Data In Valid before WR ↑ or CS ↑ (setup time) 20 — ns 63 TWRH2DTIWR ↑ or CS ↑ to Data–In Invalid (hold time) PIC18FXXXX 20 — ns PIC18LFXXXX 35 — ns VDD = 2.0V 64 TRDL2DTVRD ↓ and CS ↓ to Data–Out Valid — 80 ns 65 TRDH2DTIRD ↑ or CS ↓ to Data–Out Invalid 10 30 ns 66 TIBFINH Inhibit of the IBF Flag bit being Cleared from WR ↑ or CS ↑ —3 TCY RE2/CS RE0/RD RE1/WR RD<7:0> 62 63 64 65 |
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