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PIC18F4580-E/ML 데이터시트(PDF) 131 Page - Microchip Technology |
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PIC18F4580-E/ML 데이터시트(HTML) 131 Page - Microchip Technology |
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131 / 490 page ![]() © 2009 Microchip Technology Inc. DS39637D-page 131 PIC18F2480/2580/4480/4580 REGISTER 10-11: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP CMIP(1) — EEIP BCLIP HLVDIP TMR3IP ECCP1IP(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 CMIP: Comparator Interrupt Priority bit(1) 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as ‘0’ bit 4 EEIP: Data EEPROM/Flash Write Operation Interrupt Priority bit 1 = High priority 0 = Low priority bit 3 BCLIP: Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 HLVDIP: High/Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 ECCP1IP: CCP1 Interrupt Priority bit(2) 1 = High priority 0 = Low priority Note 1: This bit is available in PIC18F4X80 devices and reserved in PIC18F2X80 devices. 2: This bit is available in PIC18F4X80 devices only. |
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