68HC705SP7 datasheet(158/230 Pages) FREESCALE

158 / 230 page

Programmable Timer

General Release Specification

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

Programmable Timer

11.3 Timer Registers (TMRH and TMRL)

The functional block diagram of the 16-bit free-running timer counter and

timer registers is shown in Figure 11-2. The timer registers include a

transparent buffer latch on the LSB of the 16-bit timer counter.

Figure 11-2. Programmable Timer Block Diagram

The timer registers (TMRH and TMRL) shown in Figure 11-3 are read-

only locations which contain the current high and low bytes of the 16-bit

free-running counter. Writing to the timer registers has no effect. Reset

of the device presets the timer counter to $FFFC.

TMRH ($0018)

TMR LSB

16-BIT COUNTER

÷ 4

INTERNAL

(OSC

÷ 2)

TIMER CONTROL REG.

TIMER

REQUEST

OVERFLOW (TOF)

RESET

CLOCK

INTERRUPT

TMRL ($0019)

TIMER STATUS REG.

$0012

$0013

INTERNAL

($FFFC)

DATA

READ

TMRH

READ

TMRL

READ

LATCH

BUS

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

68HC705SP7 데이터시트(PDF) 158 Page - Freescale Semiconductor, Inc

68HC705SP7 데이터시트(HTML) 158 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL