68HC705SP7 datasheet(166/230 Pages) FREESCALE

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Programmable Timer

General Release Specification

MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0

Programmable Timer

A software example of this procedure is shown in Table 11-1.

11.7 Timer Control Register (TCR)

The timer control register shown in Figure 11-10, performs the following

functions:

•

Enables input capture interrupts

•

Enables output compare interrupts

•

Enables timer overflow interrupts

•

Controls the active edge polarity of the TCAP signal

•

Controls the active level of the TCMP output

Reset clears all the bits in the TCR with the exception of the IEDG bit

which is unaffected.

Table 11-1. Output Compare Initialization Example

...

SEI

...

STA

LDA

STX

...

CLI

OCRH

TSR

OCRL

DISABLE INTERRUPTS

.....

INHIBIT OUTPUT COMPARE

ARM OCF FLAG FOR CLEARING

READY FOR NEXT COMPARE, OCF CLEARED

.....

ENABLE INTERRUPTS

$0012

Bit 7

654321

Bit 0

Read:

ICIE

OCIE

TOIE

000

IEDG

OLVL

Write:

Reset:

000000

= Unimplemented

U = Unaffected

Figure 11-10. Timer Control Register (TCR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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