MAC7200 datasheet(301/976 Pages) FREESCALE

301 / 976 page

The SPP DMA Controller Module (SPP_DMA2)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

223

range of the priority value is limited to the values of 0 through 15. See Figure 12-2 and Table 12-5 for the

DMACR definition.

Channel preemption is enabled on a per channel basis by setting the ECP bit in the DCHPRIn register.

Channel preemption allows the executing channel’s data transfers to be temporarily suspended in favor of

starting a higher priority channel. Once the preempting channel has completed all of its minor loop data

transfers, the preempted channel is restored and resumes execution. After the restored channel completes

one read/write sequence, it is again eligible for preemption. If any higher priority channel is requesting

service, the restored channel will be suspended and the higher priority channel will be serviced. Nested

preemption (attempting to preempt a preempting channel) is not supported. Once a preempting channel

begins execution, it cannot be preempted. Preemption is only available when fixed arbitration is selected

for channel arbitration modes. See Figure 12-16 and Table 12-19 for the DCHPRIn definition.

12.2.4.1.16

Transfer Control Descriptor (TCD)

Each channel requires a 32-byte transfer control descriptor for defining the desired data movement

operation. The TCD structure was previously discussed in detail in Section 12.2.2, “Features.” The

channel descriptors are stored in the local memory in sequential order: channel 0, channel 1, ... channel

[n-1]. The definitions of the TCD are presented as eight 32-bit values. Table 12-20 is a 32-bit view of the

basic TCD structure.

76543210

R ECP

CHPRI[3:0]

Reset

******

= Unimplemented,

= defaults to channel number (n) after reset

Figure 12-16. DMA Channel n Priority (DCHPRIn) Register

Table 12-19. DCHPRIn Field Descriptions

Field

Description

ECP

Enable Channel Preemption.

0 Channel n cannot be suspended by a higher priority channel’s service request.

1 Channel n can be temporarily suspended by the service request of a higher priority channel.

6-4

Reserved, should be cleared.

3–0

CHPRI[3:0]

Channel n Arbitration Priority. Channel priority when fixed-priority arbitration is enabled.

Table 12-20. TCDn 32-bit Memory Structure

DMA Offset

TCDn Field

0x1000 + (32 x n) + 0x00

Source Address (saddr)

MAC7200 데이터시트(PDF) 301 Page - Freescale Semiconductor, Inc

MAC7200 데이터시트(HTML) 301 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL