MAC7200 datasheet(175/976 Pages) FREESCALE

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Debug External Pins

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

8.4.3

Debug Reset

See Section 6.4, “Debug Reset” for a complete description of debug logic resets.

8.5

Debug External Pins

8.6

Debug Bus Aborts

There is no bus interface to any of the debug logic.

8.7

Debug Differences from MAC71xx

See Section 11.7, “Nexus Differences from MAC71xx”.

8.8

Debug Application Usage

The Debug Mode of the system is completely determined by the Debug state of the ARM7 core. Therefore,

please refer to the ARM7 documentation for all of the possible ways for the ARM7 core to enter the debug

state.

Table 8-2. Debug External Pins

Description

TCK JTAG Input Clock. This pin provides the test clock input to synchronize the device’s test

logic. TCK is independent of the processor clock, and is used only as the reference clock

for the TMS, TDI and TDO pins. During and after a system reset, this pin will be configured

as an input with an internal pull-down active on this signal. This pull-down is implemented

using active elements, and is approximately equivalent to a 20KOhm resistor under typical

operating conditions.

TMS JTAG Input Mode Select. This pin is used to input the test mode to sequence the TAP

controller’s state machine. The pin is sampled on the rising edge of the TCK pin. During

and after a system reset, this pin will be configured as an input with an internal pull-up

active on this signal. This pull-up is implemented using active elements, and is

approximately equivalent to a 20KOhm resistor under typical operating conditions.

TDI JTAG Serial Data In. This serial pin is sampled in the device on the rising edge of the TCK

pin. During and after a system reset, this pin will be configured as an input with an internal

pull-up active on this signal. This pull-up is implemented using active elements, and is

approximately equivalent to a 20KOhm resistor under typical operating conditions.

TDO JTAG Serial Data Out. This pin is a three-state test data output pin that is actively driven in

the shift-IR and shift-DR controller states. The pin state changes on the falling edge of the

TCK pin. During and after a system reset, this pin will be configured as an output with

maximum slew rate enabled.

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