AT90PWM2 datasheet(262/361 Pages) ATMEL

262 / 361 page

262

4317J–AVR–08/10

AT90PWM2/3/2B/3B

To work with the 10-bit DAC, two registers have to be updated. In order to avoid intermediate

value, the DAC input values which are really converted into analog signal are buffering into

unreachable registers. In normal mode, the update of the shadow register is done when the reg-

ister DACH is written.

In case DAATE bit is set, the DAC input values will be updated on the trigger event selected

through DATS bits.

In order to avoid wrong DAC input values, the update can only be done after having written

respectively DACL and DACH registers. It is possible to work on 8-bit configuration by only writ-

ing the DACH value. In this case, update is done each trigger event.

In case DAATE bit is cleared, the DAC is in an automatic update mode. Writing the DACH regis-

ter automatically update the DAC input values with the DACH and DACL register values.

It means that whatever is the configuration of the DAATE bit, changing the DACL register has no

effect on the DAC output until the DACH register has also been updated. So, to work with 10

bits, DACL must be written first before DACH. To work with 8-bit configuration, writing DACH

allows the update of the DAC.

AT90PWM2 데이터시트(PDF) 262 Page - ATMEL Corporation