PIC18F23K22-ESLASHML datasheet(123/496 Pages) MICROCHIP

123 / 496 page

 2010 Microchip Technology Inc.

Preliminary

DS41412C-page 123

PIC18(L)F2X/4XK22

9.6

PIE Registers

The PIE registers contain the individual enable bits for

the peripheral interrupts. Due to the number of

peripheral interrupt sources, there are five Peripheral

Interrupt Enable registers (PIE1, PIE2, PIE3, PIE4 and

PIE5). When IPEN = 0, the PEIE/GIEL bit must be set to

enable any of these peripheral interrupts.

PIE1: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 1

U-0

R/W-0

—

ADIE

RC1IE

TX1IE

SSP1IE

CCP1IE

TMR2IE

TMR1IE

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

Unimplemented: Read as ‘0’.

bit 6

ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D interrupt

0 = Disables the A/D interrupt

bit 5

RC1IE: EUSART1 Receive Interrupt Enable bit

1 = Enables the EUSART1 receive interrupt

0 = Disables the EUSART1 receive interrupt

bit 4

TX1IE: EUSART1 Transmit Interrupt Enable bit

1 = Enables the EUSART1 transmit interrupt

0 = Disables the EUSART1 transmit interrupt

bit 3

SSP1IE: Master Synchronous Serial Port 1 Interrupt Enable bit

1 = Enables the MSSP1 interrupt

0 = Disables the MSSP1 interrupt

bit 2

CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt

0 = Disables the CCP1 interrupt

bit 1

TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt

0 = Disables the TMR2 to PR2 match interrupt

bit 0

TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt

0 = Disables the TMR1 overflow interrupt

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