5000 datasheet(103/104 Pages) INTEL

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Dual-Core Intel® Xeon® Processor 5000 Series Datasheet

103

Debug Tools Specifications

Please refer to the eXtended Debug Port: Debug Port Design Guide for UP and DP

Platforms and the appropriate platform design guidelines for information regarding

debug tool specifications. Section 1.3 provides collateral details.

9.1

Debug Port System Requirements

The Dual-Core Intel Xeon Processor 5000 series debug port is the command and

control interface for the In-Target Probe (ITP) debugger. The ITP enables run-time

control of the processors for system debug. The debug port, which is connected to the

FSB, is a combination of the system, JTAG and execution signals. There are several

mechanical, electrical and functional constraints on the debug port that must be

followed. The mechanical constraint requires the debug port connector to be installed in

the system with adequate physical clearance. Electrical constraints exist due to the

mixed high and low speed signals of the debug port for the processor. While the JTAG

signals operate at a maximum of 75 MHz, the execution signals operate at the common

clock FSB frequency. The functional constraint requires the debug port to use the JTAG

system via a handshake and multiplexing scheme.

In general, the information in this chapter may be used as a basis for including all run-

control tools in Dual-Core Intel Xeon Processor 5000 series-based system designs,

including tools from vendors other than Intel.

Note:

The debug port and JTAG signal chain must be designed into the processor board to

utilize the XDP for debug purposes except for interposer solutions.

9.2

Target System Implementation

9.2.1

System Implementation

Specific connectivity and layout guidelines for the Debug Port are provided in the

eXtended Debug Port: Debug Port Design Guide for UP and DP Platforms and the

appropriate platform design guidelines.

9.3

Logic Analyzer Interface (LAI)

Intel is working with two logic analyzer vendors to provide logic analyzer interfaces

(LAIs) for use in debugging Dual-Core Intel Xeon Processor 5000 series systems.

Tektronix and Agilent should be contacted to obtain specific information about their

logic analyzer interfaces. The following information is general in nature. Specific

information must be obtained from the logic analyzer vendor.

Due to the complexity of Dual-Core Intel Xeon Processor 5000 series-based

multiprocessor systems, the LAI is critical in providing the ability to probe and capture

FSB signals. There are two sets of considerations to keep in mind when designing a

Dual-Core Intel Xeon Processor 5000 series-based system that can make use of an LAI:

mechanical and electrical.

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