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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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I.MX27L 데이터시트(PDF) 5 Page - Freescale Semiconductor, Inc |
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I.MX27L 데이터시트(HTML) 5 Page - Freescale Semiconductor, Inc |
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5 / 152 page  i.MX27 and i.MX27L Data Sheet, Rev. 1.7 Freescale Semiconductor 5 Functional Description and Application Information The ARM926EJ-S processor provides support for external coprocessors enabling floating-point or other application-specific hardware acceleration to be added. The ARM926EJ-S processor implements ARM architecture version 5TEJ. The four alternate bus master ports on the ARM926 Platform, which are connected directly to master ports of the MAX, are designed to support connections to multiple AHB masters external to the platform. An external arbitration AHB control module is needed if multiple external masters are desired to share an ARM926 Platform alternate bus master port. However, the alternate bus master ports on the platform support seamless connection to a single master with no external interface logic required. A primary AHB MUX (PAHBMUX) module performs address decoding, read data muxing, bus watchdog, and other miscellaneous functions for the primary AHB within the platform. A clock control module (CLKCTL) is provided to support a power-conscious design methodology, as well as implementation of several clock synchronization circuits. 2.1.1 Memory System The ARM926EJ-S complex includes 16-Kbyte Instruction and 16-Kbyte Data caches. The embedded 45-Kbyte SRAM (VRAM) can be used to avoid external memory accesses or it can be used for applications. There is also a 24-Kbyte ROM for bootstrap code. 2.2 Module Inventory Table 2 shows an alphabetical listing of the modules in the i.MX27/MX27L multimedia applications processors. A cross-reference to each module’s section and page number goes directly to a more detailed module description for additional information. Table 2. Digital and Analog Modules Block Mnemonic Block Name Functional Grouping Brief Description Section/ Page 1-Wire® 1-Wire Interface Connectivity Peripheral The 1-Wire module provides bi-directional communication between the ARM926EJ-S and the Add-Only-Memory EPROM (DS2502). The 1-Kbit EPROM is used to hold information about battery and communicates with the ARM926 Platform using the IP interface. 2.3.1/9 AIPI AHB-Lite IP Interface Module Bus Control The AIPI acts as an interface between the ARM Advanced High-performance Bus Lite. (AHB-Lite) and lower bandwidth peripherals that conforms to the IP Bus specification, Rev 2.0. 2.3.2/10 AITC ARM9EJ-S Interrupt Controller Bus Control AITC is connected to the primary AHB as a slave device. It generates the normal and fast interrupts to the ARM926EJ-S processor. 2.3.3/10 ARM926EJS ARM926EJ-S CPU The ARM926EJ-S (ARM926) is a member of the ARM9 family of general-purpose microprocessors targeted at multi-tasking applications. 2.3.4/10 ATA Advanced Technology(AT) Attachment Connectivity Peripheral The ATA block is an AT attachment host interface. It interfaces with IDE hard disc drives and ATAPI optical disc drives. 2.3.5/11 |
유사한 부품 번호 - I.MX27L_11 |
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유사한 설명 - I.MX27L_11 |
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