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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PCM5102PWR 데이터시트(PDF) 11 Page - Texas Instruments |
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PCM5102PWR 데이터시트(HTML) 11 Page - Texas Instruments |
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11 / 31 page  tSCKH System Clock (SCK) tSCKL "L" "H" 0.3*DVDD 0.7*DVDD tSCY PCM5100, PCM5101, PCM5102 www.ti.com SLAS764 – MAY 2011 System Clock Input The PCM510x requires a system clock for operating the digital interpolation filters and advanced segment DAC modulators. The system clock is applied at the SCK input (pin 12) and supports up to 50MHz. The PCM510x has a system clock detection circuit that automatically senses which frequency the system clock is operating. Common audio sampling frequencies of 8kHz, 16kHz, 32kHz - 44.1kHz - 48kHz, 88.2kHz - 96kHz, 176.4kHz -192kHz, and 384kHz with ±4% tolerance are supported. The sampling frequency detector sets the clock for the digital filter, Delta Sigma Modulator (DSM) and the Negative Charge pump (NCP) automatically. Table 3 shows examples of system clock frequencies for common audio sampling rates. SCK rates that are not common to standard audio clocks, between 1MHz and 50MHz, are only supported in the PCM512x and PCM514x devices ’ software mode, by configuring various registers. This allows the device to become a clock master and drive the host ’s serial port with LRCK and BCK, from a non audio related clock (e.g. using 12MHz to generate 44.1kHz (LRCK) and 2.8224MHz (BCK) ). Figure 12 shows the timing requirements for the system clock input. For optimal performance, it is important to use a clock source with low phase jitter and noise. Table 3. System Master Clock Inputs for Audio Related Clocks System Clock Frequency (fSCK) (MHz) Sampling Frequency 64 fS 128 fS 192 fS 256 fS 384 fS 512 fS 768 fS 1024 fS 1152 fS 1536 fS 2048 fS 3072 fS 8 kHz –(1) 1.0240(2) 1.5360(2) 2.0480 3.0720 4.0960 6.1440 8.1920 9.2160 12.2880 16.3840 24.5760 16 kHz –(1) 2.0480(2) 3.0720(2) 4.0960 6.1440 8.1920 12.2880 16.3840 18.4320 24.5760 36.8640 49.1520 32 kHz –(1) 4.0960(2) 6.1440(2) 8.1920 12.2880 16.3840 24.5760 32.7680 36.8640 49.1520 –(1) –(1) 44.1 kHz –(1) 5.6488(2) 8.4672(2) 11.2896 16.9344 22.5792 33.8688 45.1584 –(1) –(1) –(1) –(1) 48 kHz –(1) 6.1440(2) 9.2160(2) 12.2880 18.4320 24.5760 36.8640 49.1520 –(1) –(1) –(1) –(1) 88.2 kHz –(1) 11.2896(2) 16.9344 22.5792 33.8688 45.1584 –(1) –(1) –(1) –(1) –(1) –(1) 96 kHz –(1) 12.2880(2) 18.4320 24.5760 36.8640 49.1520 –(1) –(1) –(1) –(1) –(1) –(1) 176.4 kHz –(1) 22.5792 33.8688 45.1584 –(1) –(1) –(1) –(1) –(1) –(1) –(1) –(1) 192 kHz –(1) 24.5760 36.8640 49.1520 –(1) –(1) –(1) –(1) –(1) –(1) –(1) –(1) 384 kHz 24.5760 49.1520 –(1) –(1) –(1) –(1) –(1) –(1) –(1) –(1) –(1) –(1) (1) This system clock rate is not supported for the given sampling frequency. (2) This system clock rate is supported by PLL mode. Figure 12. Timing Requirements for SCK Input Table 4. Timing Requirements for SCK Input Parameters Min Max Unit tSCY System clock pulse cycle time 20 1000 ns tSCKH System clock pulse width, High 8 ns tSCKL System clock pulse width, Low 8 ns Copyright © 2011, Texas Instruments Incorporated 11 |
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