PCM5100, PCM5101, PCM5102

SLAS764

– MAY 2011

www.ti.com

System Clock PLL mode

This reduces the need for a high frequency SCK, making PCB layout easier, and reduces high frequency

electromagnetic interference.

The device starts up expecting an external SCK input, but if BCK and LRCK start correctly without SCK for 16

successive LRCK periods, then the internal PLL will start to generate internal SCK from BCK reference

automatically. In the PCM510x, the internal PLL is disabled when an external SCK is supplied; specific BCK

rates are required to generate an appropriate master clock.

Table 5 describes the minimum and maximum BCK per LRCK for the integrated PLL to automatically generate

an internal SCK.

Table 5. BCK Rates (MHz) by LRCK Sample Rate for

PCM510x PLL Operation

Sample f (kHz)

32

48

64

8

-

-

-

16

-

-

1.024

32

1.024

1.536

2.048

44.1

1.4112

2.1168

2.8224

48

1.536

2.304

3.072

96

3.072

4.608

6.144

192

6.144

9.216

12.288

384

12.288

18.432

24.576

Audio Data Interface

Audio Serial Interface

The audio interface port is a 3-wire serial port. It includes LRCK (pin 15), BCK (pin 13), and DIN (pin 14). BCK is

the serial audio bit clock, and it is used to clock the serial data present on DIN into the serial shift register of the

audio interface. Serial data is clocked into the PCM510x on the rising edge of BCK. LRCK is the serial audio

left/right word clock.

Table 6. PCM510x Audio Data Formats, Bit Depths and Clock Rates

MAX LRCK

CONTROL MODE

FORMAT

DATA BITS

128

– 3072

Up to 192kHz

64, 48, 32

(

≤50MHz)

Hardware Control

32, 24, 20, 16

384kHz

64, 128

64, 48, 32

The PCM510x requires the synchronization of LRCK and system clock, but does not need a specific phase

relation between LRCK and system clock.

If the relationship between LRCK and system clock changes more than

±5 SCK, internal operation is initialized

within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between

LRCK and system clock is completed.

If the relationship between LRCK and BCK are invalid more than 4 LRCK periods, internal operation is initialized

within one sample period and analog outputs are forced to the bipolar zero level until resynchronization between

LRCK and BCK is completed.

12

Copyright

© 2011, Texas Instruments Incorporated