전자부품 데이터시트 검색엔진 |
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LH540203 데이터시트(PDF) 13 Page - Sharp Corporation |
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LH540203 데이터시트(HTML) 13 Page - Sharp Corporation |
13 / 17 page TIMING DIAGRAMS (cont’d) VALID DATA IN RPE t WEF t REF t WLZ t A t 540203-8 W R EF D0 - D8 Q0 - Q8 VALID DATA OUT NOTES: 1. tRPE = tRPW 2. tRPE: Effective Read Pulse Width after Empty Flag HIGH. 3. The Data Out pins (D0 - D8) are forced into a high-impedance state whenever EF = LOW. Figure 14. Read Data Flow-Through WPF t 540203-9 R W FF t WFF t RFF t DH t DS t A D0 - D8 Q0 - Q8 NOTES: 1. tWPF = tWPW. 2. tWPF: Effective Write Pulse Width after Full Flag HIGH. VALID DATA IN VALID DATA OUT Figure 15. Write Data Flow-Through CMOS 2048 × 9 Asynchronous FIFO LH540203 13 |
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