INTEDG datasheet(323/478 Pages) MICROCHIP

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 2010-2012 Microchip Technology Inc.

DS41414D-page 323

PIC16(L)F1946/47

25.5.2

SYNCHRONOUS SLAVE MODE

The following bits are used to configure the EUSART

for Synchronous slave operation:

• SYNC = 1

• CSRC = 0

• SREN = 0 (for transmit); SREN = 1 (for receive)

• CREN = 0 (for transmit); CREN = 1 (for receive)

• SPEN = 1

Setting the SYNC bit of the TXxSTA register configures

the device for synchronous operation. Clearing the

CSRC bit of the TXxSTA register configures the device as

a slave. Clearing the SREN and CREN bits of the

RCxSTA register ensures that the device is in the

Transmit mode, otherwise the device will be configured to

receive. Setting the SPEN bit of the RCxSTA register

enables the EUSART. If the RXx/DTx or TXx/CKx pins

are shared with an analog peripheral the analog I/O

functions must be disabled by clearing the corresponding

ANSEL bits.

RXx/DTx and TXx/CKx pin output drivers must be

disabled by setting the corresponding TRIS bits.

25.5.2.1

EUSART Synchronous Slave

Transmit

The operation of the Synchronous Master and Slave

modes

are

identical

(see

Section 25.5.1.3

“Synchronous Master Transmission”), except in the

case of the Sleep mode.

If two words are written to the TXxREG and then the

SLEEP instruction is executed, the following will occur:

The first character will immediately transfer to

the TSR register and transmit.

The second word will remain in TXxREG

The TXxIF bit will not be set.

After the first character has been shifted out of

TSR, the TXxREG register will transfer the

second character to the TSR and the TXxIF bit

will now be set.

If the PEIE and TXxIE bits are set, the interrupt

will wake the device from Sleep and execute the

next instruction. If the GIE bit is also set, the

program will call the Interrupt Service Routine.

25.5.2.2

Synchronous Slave Transmission

Set-up:

Set the SYNC and SPEN bits and clear the

CSRC bit.

Set the RXx/DTx and TXx/CKx TRIS controls to

‘1’.

Clear the CREN and SREN bits.

If using interrupts, ensure that the GIE and PEIE

bits of the INTCON register are set and set the

TXxIE bit.

If 9-bit transmission is desired, set the TX9 bit.

Enable transmission by setting the TXEN bit.

If 9-bit transmission is selected, insert the Most

Significant bit into the TX9D bit.

Start transmission by writing the

Least

Significant 8 bits to the TXxREG register.

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