STM32F407IGH6 datasheet(114/185 Pages) STMICROELECTRONICS

114 / 185 page

Electrical characteristics

STM32F405xx, STM32F407xx

114/185

DocID022152 Rev 4

Figure 38. Recommended NRST pin protection

1. The reset network protects the device against parasitic resets.

2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in

Table 50. Otherwise the reset is not taken into account by the device.

5.3.18

TIM timer characteristics

The parameters given in Table 51 and Table 52 are guaranteed by design.

Refer to Section 5.3.16: I/O port characteristics for details on the input/output alternate

function characteristics (output compare, input capture, external clock, PWM output).

Table 50. NRST pin characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VIL(NRST)(1)

1. Guaranteed by design, not tested in production.

NRST Input low level voltage

TTL ports

2.7 V

≤ VDD

≤ 3.6 V

0.8

VIH(NRST)(1) NRST Input high level voltage

VIL(NRST)(1) NRST Input low level voltage

CMOS ports

1.8 V

≤ VDD

≤ 3.6 V

-0.3VDD

VIH(NRST)(1) NRST Input high level voltage

0.7VDD

Vhys(NRST)

NRST Schmitt trigger voltage

hysteresis

-200

RPU

Weak pull-up equivalent resistor(2)

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to

the series resistance must be minimum

(~10% order)

VIN = VSS

VF(NRST)(1) NRST Input filtered pulse

100

VNF(NRST)(1) NRST Input not filtered pulse

VDD > 2.7 V

300

TNRST_OUT Generated reset pulse duration

Internal

Reset source

µs

ai14132c

STM32Fxxx

RPU

NRST(2)

VDD

Filter

Internal Reset

0.1 μF

External

reset circuit(1)

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