DSPIC33FJMC202ESS datasheet(285/330 Pages) MICROCHIP

285 / 330 page

DS70283K-page 285

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

25.2

AC Characteristics and Timing

Parameters

The information contained in this section defines

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

AC characteristics and timing parameters for high

temperature

devices.

However,

all

timing

specifications in this section are the same as those in

Section 24.2 “AC Characteristics and Timing

Parameters”, with the exception of the parameters

listed in this section.

Parameters in this section begin with an H, which

denotes High temperature. For example, parameter

OS53 in Section 24.2 “AC Characteristics and

Timing Parameters” is the Industrial and Extended

temperature equivalent of HOS53.

TABLE 25-8:

TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

FIGURE 25-1:

LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

TABLE 25-9:

PLL CLOCK TIMING SPECIFICATIONS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature

-40°C

≤TA ≤+150°C for High Temperature

Operating voltage VDD range as described in Table 25-1.

CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

Operating temperature

-40°C

≤TA ≤+150°C for High Temperature

Param

No.

Symbol

Characteristic

Min

Typ

Max

Units

Conditions

HOS53

DCLK

CLKO Stability (Jitter)(1)

-5

0.5

Measured over 100 ms

period

Note 1: These parameters are characterized by similarity, but are not tested in manufacturing. This specification is

based on clock cycle by clock cycle measurements. To calculate the effective jitter for individual time

bases or communication clocks use this formula:

VDD/2

VSS

RL =464

CL = 50 pF for all pins except OSC2

15 pF for OSC2 output

Load Condition 1 – for all pins except OSC2

Load Condition 2 – for OSC2

Peripheral Clock Jitter

DCLK

FOSC

Peripheral Bit Rate Clock

--------------------------------------------------------------

⎝⎠

⎛⎞

------------------------------------------------------------------------

For example: Fosc = 32 MHz, DCLK = 5%, SPI bit rate clock, (i.e., SCK) is 2 MHz.

SPI SCK Jitter

DCLK

32 MHz

2 MHz

--------------------

⎝⎠

⎛⎞

------------------------------

----------

--------

1.25%

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