DSPIC33FJMC202ESS datasheet(310/330 Pages) MICROCHIP

310 / 330 page

dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304

DS70283K-page 310

Revision C (June 2008)

This revision includes minor typographical and

formatting changes throughout the data sheet text.

The major changes are referenced by their respective

section in the following table.

TABLE A-1:

MAJOR SECTION UPDATES

Section Name

Update Description

“High-Performance, 16-bit Digital

Signal Controllers”

Added Extended Interrupts column to Remappable Peripherals in the

Controller Families table and Note 3 (see Table 1).

Added Note 1 to all pin diagrams, which references RPn pin usage by

remappable peripherals (see “Pin Diagrams”).

Section 1.0 “Device Overview”

Changed PORTA pin name from RA15 to RA10 (see Table 1-1).

Section 4.0 “Memory Organization” Added SFR definitions (ACCAL, ACCAH, ACCAU, ACCBL, ACCBH, and

ACCBU) to the CPU Core Register Map (see Table 4-1).

Updated Reset value for CORCON (see Table 4-1).

Updated Reset values for the following SFRs: IPC1, IPC3-IPC5, IPC7,

IPC16, and INTTREG (see Table 4-4).

Updated all SFR names in QEI1 Register Map (see Table 4-10).

Updated the bit range for AD1CON3 from ADCS<5:0> to ADCS<7:0>) (see

Table 4-14 and Table 4-15).

Updated the Reset value for CLKDIV in the System Control Register Map

(see Table 4-23).

Section 6.0 “Resets”

Entire section was replaced to maintain consistency with other dsPIC33F

data sheets.

Section 8.0 “Oscillator

Configuration”

Removed the first sentence of the third clock source item (External Clock) in

Section 8.1.1.2 “Primary”.

Updated the default bit values for DOZE and FRCDIV in the Clock Divisor

Added the center frequency in the OSCTUN register for the FRC Tuning bits

(TUN<5:0>) value 011111 and updated the center frequency for bits value

011110 (see Register 8-4).

Section 9.0 “Power-Saving

Features”

Added the following two registers:

• PMD1: Peripheral Module Disable Control Register 1

• PMD2: Peripheral Module Disable Control Register 2

• PMD3: Peripheral Module Disable Control Register 3

Section 10.0 “I/O Ports”

Added paragraph and Table 10-1 to Section 10.2 “Open-Drain

Configuration”, which provides details on I/O pins and their functionality.

Removed the following sections, which are now available in the related

section of the dsPIC33F/PIC24H Family Reference Manual:

• 9.4.2 “Available Peripherals”

• 9.4.3.3 “Mapping”

• 9.4.5 “Considerations for Peripheral Pin Selection”

Section 14.0 “Output Compare”

Replaced sections 13.1, 13.2, and 13.3 and related figures and tables with

entirely new content.

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