KA555

5

Figure 1 illustrates a monos table circuit. In this mode, the timer generates a fixed pulse whenever the trigger voltage falls

below Vcc/3. When the trigger pulse voltage applied to the #2 pin falls below Vcc/3 while the timer output is low, the timer's

internal flip-flop turns the discharging Tr. off and causes the timer output to become high by charging the external capacitor

C1and setting the flip-flop output at the same time.

When the applied voltage to the capacitor C1 reaches 2Vcc/3, the comparator on the trigger terminal resets the flip-flop,

turning the discharging Tr. on. At this time, C1 begins to discharge and the timer output converts to low.

In this way, the timer operating in monos table repeats the above process. Figure 2 shows the time constant relationship based

It must be noted that, for normal operation, the trigger pulse voltage needs to maintain a minimum of Vcc/3 before the timer

output turns low. That is, although the output remains unaffected even if a different trigger pulse is applied while the output is

high, it may be affected and the waveform not operate properly if the trigger pulse voltage at the end of the output pulse

remains at below Vcc/3. Figure 4 shows such timer output abnormality

.

2. Astable Operation

Figure 4. Waveforms of Monos table Operation (abnormal)

100m

1

10

100

1k

10k

100k

1E-3

0.01

0.1

1

10

100

(R

Frequency(Hz)

Figure 5. Astable Circuit

Figure 6. Capacitance and Resistance vs. Frequency

1

5

6

7

8

4

2

3

RESET

Vcc

DISCH

THRES

CONT

GND

OUT

TRIG

+Vcc

C1

C2