전자부품 데이터시트 검색엔진 |
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NE555 데이터시트(PDF) 4 Page - Fairchild Semiconductor |
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NE555 데이터시트(HTML) 4 Page - Fairchild Semiconductor |
4 / 14 page LM555/NE555/SA555 4 4 4 4 Application Information Application Information Application Information Application Information Table 1 below is the basic operating table of 555 timer: When the low signal input is applied to the reset terminal, the timer output remains low regardless of the threshold voltage or the trigger voltage. Only when the high signal is applied to the reset terminal, the timer's output changes according to threshold voltage and trigger voltage. When the threshold voltage exceeds 2/3 of the supply voltage while the timer output is high, the timer's internal discharge Tr. turns on, lowering the threshold voltage to below 1/3 of the supply voltage. During this time, the timer output is maintained low. Later, if a low signal is applied to the trigger voltage so that it becomes 1/3 of the supply voltage, the timer's internal discharge Tr. turns off, increasing the threshold voltage and driving the timer output again at high. 1. Monostable Operation 1. Monostable Operation 1. Monostable Operation 1. Monostable Operation Table 1. Basic Operating Table Table 1. Basic Operating Table Table 1. Basic Operating Table Table 1. Basic Operating Table Threshold Voltage Threshold Voltage Threshold Voltage Threshold Voltage (V (V (V (Vth th th th)(PIN 6) )(PIN 6) )(PIN 6) )(PIN 6) Trigger Voltage Trigger Voltage Trigger Voltage Trigger Voltage (V (V (V (Vtr tr tr tr)(PIN 2) )(PIN 2) )(PIN 2) )(PIN 2) Reset(PIN 4) Reset(PIN 4) Reset(PIN 4) Reset(PIN 4) Output(PIN 3) Output(PIN 3) Output(PIN 3) Output(PIN 3) Discharging Tr. Discharging Tr. Discharging Tr. Discharging Tr. (PIN 7) (PIN 7) (PIN 7) (PIN 7) Don't care Don't care Low Low ON Vth > 2Vcc / 3 Vth > 2Vcc / 3 High Low ON Vcc / 3 < Vth < 2 Vcc / 3 Vcc / 3 < Vth < 2 Vcc / 3 High - - Vth < Vcc / 3 Vth < Vcc / 3 High High OFF 10 10 10 10 -5 -5 -5 -5 10 10 10 10 -4 -4 -4 -4 10 10 10 10 -3 -3 -3 -3 10 10 10 10 -2 -2 -2 -2 10 10 10 10 -1 -1 -1 -1 10 10 10 10 0 00 0 10 10 10 10 1 11 1 10 10 10 10 2 22 2 10 10 10 10 -3 -3 -3 -3 10 10 10 10 -2 -2 -2 -2 10 10 10 10 -1 -1 -1 -1 10 10 10 10 0 00 0 10 10 10 10 1 11 1 10 10 10 10 2 22 2 Time Delay(s) Time Delay(s) Time Delay(s) Time Delay(s) Figure 1. Monoatable Circuit Figure 1. Monoatable Circuit Figure 1. Monoatable Circuit Figure 1. Monoatable Circuit Figure 2. Resistance and Capacitance vs. Figure 2. Resistance and Capacitance vs. Figure 2. Resistance and Capacitance vs. Figure 2. Resistance and Capacitance vs. Time delay(t Time delay(t Time delay(t Time delay(td d d d)))) Figure 3. Waveforms of Monostable Operation Figure 3. Waveforms of Monostable Operation Figure 3. Waveforms of Monostable Operation Figure 3. Waveforms of Monostable Operation 1 5 6 7 8 4 2 3 RESET Vcc DISCH THRES CONT GND OUT TRIG +Vcc RA C1 C2 RL Trigger |
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