전자부품 데이터시트 검색엔진 |
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ML4425 데이터시트(PDF) 11 Page - Fairchild Semiconductor |
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ML4425 데이터시트(HTML) 11 Page - Fairchild Semiconductor |
11 / 16 page PRODUCT SPECIFICATION ML4425 REV. 1.0.2 7/2/01 11 Figure 8. ML4425 Start-up Circuitry for Controlling the Align and Ramp Times CAT CAT FB A FB B FB C BACK EMF SAMPLER CRT CRT CRR – + 1.5V 750nA – + 1.5V 750nA VDD VDD CRR 500nA VDD SPEED FB TO SPEED FB FILTER CVCO RVCO VOLTAGE CONTROLLED OSCILLATOR VCO/TACH TO RESET INPUT OF COMMUTATION STATE MACHINE Run Mode (Back EMF Sensing) At the end of ramp mode the controller goes into run mode. In run mode, the back EMF sensing is enabled and commuta- tion is now under the control of the phase locked loop. Motor speed is now regulated by the speed control loop. PWM Speed Control Speed control is accomplished by setting a speed command at SPEED SET with an input voltage from 0 to 6.9V (VREF). The accuracy of the speed command is determined by the external components RVCO and CVCO. There are a number of methods that can be used to control the speed command of the ML4425. One is to use a 10k Ω potentiometer from VREF to ground with the wiper connected to SPEED SET. If SPEED SET is controlled from a microcontroller, one of its DACs can be used with VREF as its input reference. The speed command is compared with the sensed speed from SPEED FB through a transconductance error amplifier. The output of the speed error amplifier is SPEED COMP. SPEED COMP is clamped between one diode drop above 3.9V (approximately 4.6V) and one diode drop below 1.7V (approximately 1V) to prevent speed loop “wind-up”. Speed loop compensation components are connected to this pin as shown in Figure 9. The speed loop compensation compo- nents are calculated as follows: Where fSB is the speed loop bandwidth in Hz. Figure 9. Speed Control Loop Component Connections The voltage on SPEED COMP is compared with a ramp oscillator to create a PWM duty cycle. The PWM ramp oscil- lator creates a sawtooth function from 1.7V to 3.9V as shown in Figure 9. A negative clamp at one diode drop below 1.7V (approximately 1V) starts the oscillator on power up. The frequency of the ramp oscillator is set by a capacitor to ground CIOS and is selected using the following equation: Where fPWM is the PWM frequency in Hz. The PWM duty cycle from the speed control loop is gated the current limit one shot that controls the LA, LB, and LC output drivers. C SC 26.9 N V MOTOR C VCO × × × f SB K e × 2.5 98.696 τm 2 f SB 2 × × + ------------------------------------------------------------------------------------------- = (9a) R SC 10 2 π f SB C SC × × --------------------------------------- = (9b) – + + – SPEED SET SPEED COMP 3.9V 1.7V 10k Ω 20kHz PWM ON/OFF FROM ILIMIT ONE-SHOT FROM SPEED FB TO GATING LOGIC & OUTPUT DRIVERS CT CT CSC RSC 1.7V VREF C T I f PWM -------------- 50 µA × 2.4V ----------------------------------- = (10) |
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