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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PIC18F2610E/SOSQTP 데이터시트(PDF) 203 Page - Microchip Technology |
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PIC18F2610E/SOSQTP 데이터시트(HTML) 203 Page - Microchip Technology |
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203 / 376 page  © 2009 Microchip Technology Inc. DS39636D-page 205 PIC18F2X1X/4X1X FIGURE 17-7: ASYNCHRONOUS RECEPTION TABLE 17-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Start bit bit 7/8 bit 1 bit 0 bit 7/8 bit 0 Stop bit Start bit Start bit bit 7/8 Stop bit RX (pin) Rcv Buffer Reg Rcv Shift Reg Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Word 1 RCREG Word 2 RCREG Stop bit Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word causing the OERR (overrun) bit to be set. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51 PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53 RCREG EUSART Receive Register 53 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53 BAUDCON ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 53 SPBRGH EUSART Baud Rate Generator Register, High Byte 53 SPBRG EUSART Baud Rate Generator Register, Low Byte 53 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. Note 1: These bits are unimplemented on 28-pin devices and read as ‘0’. |
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