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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DSPIC33FJ12GP201TE/ML 데이터시트(PDF) 139 Page - Microchip Technology |
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DSPIC33FJ12GP201TE/ML 데이터시트(HTML) 139 Page - Microchip Technology |
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139 / 242 page  © 2007 Microchip Technology Inc. Preliminary DS70264B-page 137 dsPIC33FJ12GP201/202 FIGURE 14-2: SPI MASTER/SLAVE CONNECTION FIGURE 14-3: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM FIGURE 14-4: SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM Serial Receive Buffer (SPIxRXB) LSb MSb SDIx SDOx PROCESSOR 2 (SPI Slave) SCKx SSx(1) Serial Transmit Buffer (SPIxTXB) Serial Receive Buffer (SPIxRXB) Shift Register (SPIxSR) MSb LSb SDOx SDIx PROCESSOR 1 (SPI Master) Serial Clock (SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0) Note 1: Using the SSx pin in Slave mode of operation is optional. 2: User application must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF. SCKx Serial Transmit Buffer (SPIxTXB) (MSTEN (SPIxCON1<5>) = 1) SPI Buffer (SPIxBUF)(2) SPI Buffer (SPIxBUF)(2) Shift Register (SPIxSR) SDOx SDIx dsPIC33F Serial Clock SSx SCKx Frame Sync Pulse SDIx SDOx PROCESSOR 2 SSx SCKx SDOx SDIx dsPIC33F Serial Clock SSx SCKx Frame Sync Pulse SDIx SDOx PROCESSOR 2 SSx SCKx |
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