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DSPIC33FJ06GS101TE/ML 데이터시트(PDF) 340 Page - Microchip Technology |
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DSPIC33FJ06GS101TE/ML 데이터시트(HTML) 340 Page - Microchip Technology |
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340 / 346 page  dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 DS70318D-page 338 Preliminary © 2009 Microchip Technology Inc. H High-Speed Analog Comparator ....................................... 251 High-Speed PWM ............................................................. 189 I I/O Ports ............................................................................ 145 Parallel I/O (PIO)....................................................... 145 Write/Read Timing .................................................... 147 I2C Operating Modes ...................................................... 215 Registers................................................................... 215 In-Circuit Debugger ........................................................... 260 In-Circuit Emulation........................................................... 255 In-Circuit Serial Programming (ICSP) ....................... 255, 260 Input Capture .................................................................... 183 Registers................................................................... 184 Input Change Notification.................................................. 147 Instruction Addressing Modes............................................. 63 File Register Instructions ............................................ 63 Fundamental Modes Supported.................................. 64 MAC Instructions......................................................... 64 MCU Instructions ........................................................ 63 Move and Accumulator Instructions ............................ 64 Other Instructions........................................................ 64 Instruction Set Overview ................................................................... 266 Summary................................................................... 263 Instruction-Based Power-Saving Modes ........................... 137 Idle ............................................................................ 138 Sleep......................................................................... 137 Interfacing Program and Data Memory Spaces .................. 68 Internal RC Oscillator Use with WDT ........................................................... 259 Internet Address................................................................ 331 Interrupt Control and Status Registers................................ 91 IECx ............................................................................ 91 IFSx............................................................................. 91 INTCON1 .................................................................... 91 INTCON2 .................................................................... 91 INTTREG .................................................................... 91 IPCx ............................................................................ 91 Interrupt Setup Procedures ............................................... 125 Initialization ............................................................... 125 Interrupt Disable........................................................ 125 Interrupt Service Routine .......................................... 125 Trap Service Routine ................................................ 125 Interrupt Vector Table (IVT) ................................................ 87 Interrupts Coincident with Power Save Instructions.......... 138 J JTAG Boundary Scan Interface ........................................ 255 JTAG Interface .................................................................. 260 M Memory Organization.......................................................... 33 Microchip Internet Web Site .............................................. 331 Modulo Addressing ............................................................. 65 Applicability ................................................................. 66 Operation Example ..................................................... 65 Start and End Address................................................ 65 W Address Register Selection .................................... 65 MPLAB ASM30 Assembler, Linker, Librarian ................... 272 MPLAB ICD 2 In-Circuit Debugger.................................... 273 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator .................................................... 273 MPLAB Integrated Development Environment Software.. 271 MPLAB PM3 Device Programmer .................................... 273 MPLAB REAL ICE In-Circuit Emulator System ................ 273 MPLINK Object Linker/MPLIB Object Librarian ................ 272 O Open-Drain Configuration................................................. 146 Oscillator Configuration .................................................... 127 Output Compare ............................................................... 185 P Packaging ......................................................................... 309 Details....................................................................... 311 Marking..................................................................... 309 Peripheral Module Disable (PMD) .................................... 138 PICSTART Plus Development Programmer..................... 274 Pinout I/O Descriptions (table)............................................ 15 Power-on Reset (POR)....................................................... 84 Power-Saving Features .................................................... 137 Clock Frequency and Switching ............................... 137 Program Address Space..................................................... 33 Construction ............................................................... 68 Data Access from Program Memory Using Program Space Visibility..................................... 71 Data Access from Program Memory Using Table Instructions ............................................... 70 Data Access from, Address Generation ..................... 69 Memory Maps ............................................................. 33 Table Read Instructions TBLRDH ............................................................. 70 TBLRDL.............................................................. 70 Visibility Operation...................................................... 71 Program Memory Interrupt Vector ........................................................... 34 Organization ............................................................... 34 Reset Vector............................................................... 34 R Reader Response............................................................. 332 Registers .................................................................................. 207 A/D Control Register (ADCON) ................................ 237 A/D Convert Pair Control Register 0 (ADCPC0)....... 241 A/D Convert Pair Control Register 1 (ADCPC1)....... 243 A/D Convert Pair Control Register 2 (ADCPC2)....... 246 A/D Convert Pair Control Register 3 (ADCPC3)....... 249 A/D Port Configuration Register (ADPCFG) ............. 240 A/D Status Register (ADSTAT)................................. 239 ACLKCON (Auxiliary Clock Divisor Control)............. 134 ALTDTRx (PWM Alternate Dead-Time).................... 200 CLKDIV (Clock Divisor) ............................................ 131 CMPCPNx (Comparator Control) ............................. 253 CMPDACx (Comparator DAC Control)..................... 254 CORCON (Core Control) ...................................... 26, 92 DTRx (PWMx Dead-Time)........................................ 200 FCLCONx (PWMx Fault Current-Limit Control)........ 204 I2CxCON (I2Cx Control) ........................................... 217 I2CxMSK (I2Cx Slave Mode Address Mask) ............ 221 I2CxSTAT (I2Cx Status) ........................................... 219 ICxCON (Input Capture x Control)............................ 184 IEC0 (Interrupt Enable Control 0) ............................. 103 IEC1 (Interrupt Enable Control 1) ............................. 105 IEC3 (Interrupt Enable Control 3) ............................. 106 IEC4 (Interrupt Enable Control 4) ............................. 106 IEC5 (Interrupt Enable Control 5) ............................. 107 IFS0 (Interrupt Flag Status 0) ..................................... 96 |
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