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DSPIC33FJ06GS101TE/ML 데이터시트(PDF) 114 Page - Microchip Technology |
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DSPIC33FJ06GS101TE/ML 데이터시트(HTML) 114 Page - Microchip Technology |
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114 / 346 page ![]() dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 DS70318D-page 112 Preliminary © 2009 Microchip Technology Inc. bit 2 OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 IC1IE: Input Capture Channel 1 Interrupt Enable bit(1) 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled REGISTER 7-12: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED) Note 1: These bits are unimplemented in dsPIC33FJ06GS101/102 devices. 2: These bits are unimplemented in dsPIC33FJ06GS202 devices. |
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