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STM32F217IG 데이터시트(PDF) 106 Page - STMicroelectronics

부품명 STM32F217IG
상세설명  ARM-based 32-bit MCU, 150DMIPs, up to 1 MB Flash/1284KB RAM
PDF  175 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
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STM32F217IG 데이터시트(HTML) 106 Page - STMicroelectronics

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Electrical characteristics
STM32F21xxx
106/175
DocID17050 Rev 9
6.3.17
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 48).
Unless otherwise specified, the parameters given in Table 48 are derived from tests
performed under the ambient temperature and VDD supply voltage conditions summarized
in Table 13.
Figure 37. Recommended NRST pin protection
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 48. Otherwise the reset is not taken into account by the device.
Table 48. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIL(NRST)(1) NRST input low level voltage
TTL ports
2.7 V
≤ VDD ≤ 3.6 V
--
0.8
V
VIH(NRST)(1) NRST input high level voltage
2
-
-
VIL(NRST)(1) NRST input low level voltage
CMOS ports
1.8 V
≤ VDD ≤ 3.6 V
-
-
0.3VDD
V
VIH(NRST)(1) NRST input high level voltage
0.7VDD
--
Vhys(NRST)
NRST Schmitt trigger voltage
hysteresis
-200
-
mV
RPU
Weak pull-up equivalent resistor(2)
VIN = VSS
30
40
50
k
Ω
VF(NRST)(1)
NRST Input filtered pulse
-
-
100
ns
VNF(NRST)(1) NRST Input not filtered pulse
VDD > 2.7 V
300
-
-
ns
TNRST_OUT Generated reset pulse duration
Internal Reset source
20
-
-
µs
1. Guaranteed by design, not tested in production.
2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance must be minimum
(~10% order)
.
ai14132c
STM32Fxxx
RPU
NRST(2)
VDD
Filter
Internal Reset
0.1 μF
External
reset circuit(1)



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