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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ATMEGA128A 데이터시트(PDF) 7 Page - ATMEL Corporation |
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ATMEGA128A 데이터시트(HTML) 7 Page - ATMEL Corporation |
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7 / 369 page  7 ATmega 128A [DATASHEET] Atmel-8151I-8-bit-AVR-ATmega128A_Datasheet-08/2014 Port C also serves the functions of special features of the ATmega128A as listed on page 74. In ATmega103 compatibility mode, Port C is output only, and the port C pins are not tri-stated when a reset condition becomes active. Note: The Atmel®AVR® ATmega128A is by default shipped in ATmega103 compatibility mode. Thus, if the parts are not programmed before they are put on the PCB, PORTC will be output during first power up, and until the ATmega103 compatibility mode is disabled. 2.3.6 Port D (PD7:PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri- stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATmega128A as listed on page 76. 2.3.7 Port E (PE7:PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri- stated when a reset condition becomes active, even if the clock is not running. Port E also serves the functions of various special features of the ATmega128A as listed on page 78. 2.3.8 Port F (PF7:PF0) Port F serves as the analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a Reset occurs. The TDO pin is tri-stated unless TAP states that shift out data are entered. Port F also serves the functions of the JTAG interface. In ATmega103 compatibility mode, Port F is an input Port only. 2.3.9 Port G (PG4:PG0) Port G is a 5-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri- stated when a reset condition becomes active, even if the clock is not running. Port G also serves the functions of various special features. The port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. In Atmel®AVR®ATmega103 compatibility mode, these pins only serves as strobes signals to the external memory as well as input to the 32kHz Oscillator, and the pins are initialized to PG0 = 1, PG1 = 1, and PG2 = 0 asynchronously when a reset condition becomes active, even if the clock is not running. PG3 and PG4 are oscillator pins. |
유사한 부품 번호 - ATMEGA128A_14 |
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유사한 설명 - ATMEGA128A_14 |
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