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IDT72131 데이터시트(PDF) 7 Page - Integrated Device Technology |
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IDT72131 데이터시트(HTML) 7 Page - Integrated Device Technology |
7 / 13 page 5.34 7 IDT72131, IDT72141 CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9 COMMERCIAL TEMPERATURE RANGES NOTE: 1. Once EF has gone LOW and the last bit of the final word has been shifted out, SOCP should not be clocked until EF goes HIGH. NOTE: 1. SOCP should not be clocked until EF goes HIGH. Figure 6. Empty Boundary Condition Timing 2751 drw 09 SOCP t WEF 0 1 n – 1 W EF SO t SOCEF t REFSO DATA IN (1) t SOLZ t SOPD Figure 5. Empty Flag from Last Read to First Write 2751 drw 08 SOCP t WEF LAST READ NO READ FIRST WRITE ADDITIONAL WRITES FIRST READ 0 1 n – 1 0 1 n – 1 W EF t SOPD SO VALID VALID (1) tSOCEF |
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