CMT2110/17AW

Rev 1.2 | Page 10/25

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4. Typical Application Schematics

4.1 Low-Cost Application Schematic

DATA

U1

XTAL

VDD

GND

RFO

1

2

3

5

6

X1

4

CLK

DATA

L2

L1

C2

C1

C0

VDD

DATA

CLK

J1

VDD

1

2

3

4

VDD

CMT2110/17AW

ANT

CLK

Note: Connector J1 is for

EEPROM Programming

Figure 9. Low-Cost Application Schematic

Notes:

1.

Connector J1 is a must for the CMT2110/17AW EEPROM access during development or manufacture.

2.

The general layout guidelines are listed below. For more design details, please refer to “AN101 CMT211xA Schematic and

PCB Layout Design Guideline”



Use as much continuous ground plane metallization as possible.



Use as many grounding vias (especially near to the GND pins) as possible to minimize series parasitic inductance

between the ground pour and the GND pins.



Avoid using long and/or thin transmission lines to connect the components.



Avoid placing the nearby inductors in the same orientation to reduce the coupling between them.



Place C0 as close to the CMT2110/17AW as possible for better filtering.

3.

The table below shows the BOM of 433.92/868.35 MHz Low-Cost Application. For the BOM of 315/915 MHz application,

please refer to “AN101 CMT211xA Schematic and PCB Layout Design Guideline”.

Table 8. BOM of 433.92/868.35 MHz Low-Cost Application

Designator

Descriptions

Value

Unit

Manufacturer

433.92 MHz

868.35 MHz

[1]

U1

CMT2110/17AW, Low-Cost 240 – 960 MHz

OOK Transmitter

-

-

CMOSTEK

X1

±20 ppm, SMD32*25 mm crystal

26

MHz

EPSON

C0

±20%, 0402 X7R, 25 V

0.1

uF

Murata GRM15

C1

±5%, 0402 NP0, 50 V

82

82

pF

Murata GRM15

C2

±5%, 0402 NP0, 50 V

9

3.9

pF

Murata GRM15

L1

±5%, 0603 multi-layer chip inductor

180

100

nH

Murata LQG18

L2

±5%, 0603 multi-layer chip inductor

27

8.2

nH

Murata LQG18

Note:

[1]. The 868.35 MHz Application is for CMT2117AW only.