CMT2113AW

Rev 0.8 | Page 11/26

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4.2 FCC/ETSI Compliant Application Schematic

DATA

U1

XTAL

VDD

GND

RFO

1

2

3

5

6

X1

4

CLK

DATA

C0

VDD

DATA

CLK

J1

VDD

1

2

3

4

CMT2113AW

Note: Connector J1 is for

EEPROM Programming

C1

L2

L1

C2

VDD

C3

L3

ANT

CLK

Figure 10. FCC/ETSI Compliant Application Schematic

Notes:

1.

Connector J1 is a must for the CMT2113AW EEPROM access during development or manufacture.

2.

The general layout guidelines are listed below. For more design details, please refer to “AN101 CMT211xA Schematic and

PCB Layout Design Guideline”.



Use as much continuous ground plane metallization as possible.



Use as many grounding vias (especially near to the GND pins) as possible to minimize series parasitic inductance

between the ground pour and the GND pins.



Avoid using long and/or thin transmission lines to connect the components.



Avoid placing the nearby inductors in the same orientation to reduce the coupling between them.



Place C0 as close to the CMT2113AW as possible for better filtering.

3.

The table below shows the BOM of 315/433.92 MHz FCC/ETSI Compliant Application. For the BOM of other applications,

please refer to “AN101 CMT211xA Schematic and PCB Layout Design Guideline”.

Table 8. BOM of 315/433.92 MHz FCC/ETSI Compliant Application

Designator

Descriptions

Value

Unit

Manufacturer

315 MHz

433.92 MHz

U1

CMT2113AW, low-cost 240 – 480 MHz

(G)FSK/OOK transmitter

-

CMOSTEK

X1

±20 ppm, SMD32*25 mm crystal

26

MHz

EPSON

C0

±20%, 0402 X7R, 25 V

0.1

uF

Murata GRM15

C1

±5%, 0402 NP0, 50 V

68

68

pF

Murata GRM15

C2

±5%, 0402 NP0, 50 V

18

15

pF

Murata GRM15

C3

±5%, 0402 NP0, 50 V

18

15

pF

Murata GRM15

L1

±5%, 0603 multi-layer chip inductor

180

180

nH

Murata LQG18

L2

±5%, 0603 multi-layer chip inductor

62

36

nH

Murata LQG18

L3

±5%, 0603 multi-layer chip inductor

27

18

nH

Murata LQG18