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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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L9779WD 데이터시트(PDF) 132 Page - STMicroelectronics |
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L9779WD 데이터시트(HTML) 132 Page - STMicroelectronics |
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132 / 170 page  Functional description L9779WD 132/170 DocID027452 Rev 5 Figure 82. Time circuit Table 61. Timing characteristics Symbol Parameter Min. Typ. Max. Unit tCL Cycle time 25 - - ns tsetup Data setup time 5 - - ns thold Data hold time 5 - - ns tswitch Switching time Switching time for CL, EN and SI measured between 0.1*VVDD3 and 0.9*VVDD3 -- 3 ns tCLlow CL low time 10 - - ns tCLhigh CL high time 10 - - ns tENsetup (1) 1. Enable setup time and enable hold time are validated with characterization. EN setup time (i.e. time between falling edge of EN and next falling edge of CL) 5- - ns tENhold (1) EN hold time (i.e. time between falling edge of CL and next rising edge of EN) 5- - ns tSDO /tCL data out cycle time CL_CONF1=’1’,CL_CONF0=’1’ CL_CONF1=’1’,CL_CONF0=’0’ CL_CONF1=’0’,CL_CONF0=’1’ CL_CONF1=’0’,CL_CONF0=’0’ -25% 128 64 32 16 +25% - fCL Clock range at CL L9779WD is fully functional incl. all timings as long as there is a clock at pins CLP, CLN: CL -- 40 MHz - tSDOdelay - - 160 ns |
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