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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST72561 데이터시트(PDF) 141 Page - STMicroelectronics |
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ST72561 데이터시트(HTML) 141 Page - STMicroelectronics |
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141 / 262 page  ST72561 141/262 LIN SCI SERIAL COMMUNICATION INTERFACE (LIN Mode) (Cont’d) Figure 81. SCI Block Diagram in LIN Slave Mode WAKE UP UNIT RECEIVER CONTROL SCISR TRANSMIT CONTROL TDRE TC RDRF IDLE OR/ NF FE PE SCI CONTROL INTERRUPT SCICR1 R8 T8 SCID M WAKE PCE PS PIE Received Data Register (RDR) Receive Shift Register Read Transmit Data Register (TDR) Transmit Shift Register Write RDI TDO (DATA REGISTER) SCIDR TRANSMITTER CLOCK RECEIVER CLOCK fCPU / LDIV SBK RWU RE TE ILIE RIE TCIE TIE SCICR2 LIN SLAVE BAUD RATE AUTO SYNCHRONIZATION fCPU SCICR3 LINE LASE LHIE LSF LHDF EXTENDED PRESCALER CONVENTIONAL BAUD RATE GENERATOR + /16 SCIBRR LPR7 LPR0 LIN SLAVE BAUD RATE GENERATOR 0 1 UNIT LDUM LHDM LHE LSLV |
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