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ST72561 데이터시트(PDF) 169 Page - STMicroelectronics

부품명 ST72561
상세설명  8-BIT MCU WITH FLASH OR ROM, 10-BIT ADC, 5 TIMERS, SPI, LINSCI , ACTIVE CAN
PDF  262 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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ST72561 데이터시트(HTML) 169 Page - STMicroelectronics

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LIN
SCI
 SERIAL COMMUNICATION INTERFACE (LIN Master Only) (Cont’d)
DATA REGISTER (SCIDR)
Read/Write
Reset Value: Undefined
Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.
The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 88).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 88).
BAUD RATE REGISTER (SCIBRR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:6= SCP[1:0] First SCI Prescaler
These 2 prescaling bits allow several standard
clock division ranges:
Bit 5:3 = SCT[2:0] SCI Transmitter rate divisor
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock in convention-
al Baud Rate Generator mode.
Note: this TR factor is used only when the ETPR
fine tuning factor is equal to 00h; otherwise, TR is
replaced by the (TR*ETPR) dividing factor.
Bit 2:0 = SCR[2:0] SCI Receiver rate divisor.
These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the receive rate clock in conventional
Baud Rate Generator mode.
Note: This RR factor is used only when the ERPR
fine tuning factor is equal to 00h; otherwise, RR is
replaced by the (RR*ERPR) dividing factor.
70
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
70
SCP1
SCP0
SCT2
SCT1
SCT0
SCR2
SCR1
SCR0
PR Prescaling factor
SCP1
SCP0
10
0
30
1
41
0
13
1
1
TR dividing factor
SCT2
SCT1
SCT0
10
0
0
20
0
1
40
1
0
80
1
1
16
1
0
0
32
1
0
1
64
1
1
0
128
1
1
1
RR dividing factor
SCR2
SCR1
SCR0
10
0
0
20
0
1
40
1
0
80
1
1
16
1
0
0
32
1
0
1
64
1
1
0
128
1
1
1



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