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ST72561 데이터시트(PDF) 224 Page - STMicroelectronics

부품명 ST72561
상세설명  8-BIT MCU WITH FLASH OR ROM, 10-BIT ADC, 5 TIMERS, SPI, LINSCI , ACTIVE CAN
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제조업체  STMICROELECTRONICS [STMicroelectronics]
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ST72561 데이터시트(HTML) 224 Page - STMicroelectronics

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12.3.2 Operating Conditions with Low Voltage Detector (LVD)
Subject to general operating conditions for TA.
Notes:
1. Data based on characterization results, not tested in production.
12.3.3 Auxiliary Voltage Detector (AVD) Thresholds
Subject to general operating conditions for TA.
1. Data based on characterization results, not tested in production.
Figure 120. LVD Startup Behaviour
Note: When the LVD is enabled, the MCU reaches its authorized operating voltage from a reset state.
However, in some devices, the reset signal may be undefined until VDD is approximately 2V. As a conse-
quence, the I/Os may toggle when VDD is below this voltage.
Because Flash write access is impossible below this voltage, the Flash memory contents will not be cor-
rupted.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIT+(LVD)
Reset release threshold (VDD rise)
4.0 1)
4.2
4.5
V
VIT-(LVD)
Reset generation threshold (VDD fall)
3.8
4.0
4.25
Vhys(LVD)
LVD voltage threshold hysteresis1)
VIT+(LVD)-VIT-(LVD)
150
200
250
mV
VtPOR
VDD rise time rate
1)
6
µs/V
100
ms/V
tg(VDD)
Width of filtered glitches on VDD
(which are not detected by the LVD)1)
40
ns
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VIT+(AVD)
1
⇒0 AVDF flag toggle threshold
(VDD rise)
4.4 1)
4.6
4.9
V
VIT-(AVD)
0
⇒1 AVDF flag toggle threshold
(VDD fall)
4.2
4.4
4.651)
Vhys(AVD)
AVD voltage threshold hysteresis
VIT+(AVD)-VIT-(AVD)
250
mV
∆V
IT-
Voltage drop between AVD flag set
and LVD reset activated
VIT-(AVD)-VIT-(LVD)
450
mV
5V
2V
VIT+
LVD RESET
V D
D
t
Reset state
in this area
not defined



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