ST7MC1K2TC datasheet(208/308 Pages) STMICROELECTRONICS

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MOTOR CONTROLLER (Cont’d)

INTERRUPT STATUS REGISTER (MISR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = PUI: PWM Update Interrupt flag.

This bit is set by hardware when all the PWM

Compare register are transferred from the preload

to the active registers. The corresponding interrupt

allows the user to refresh the preload registers be-

fore the next PWM update event defined with

MREP register.

0: No PWM Update interrupt pending

1: PWM Update Interrupt pending

Bit 6 = RPI: Ratio Increment interrupt flag.

Autoswitched mode (SWA bit =1):

0: No R+ interrupt pending

1: R+ Interrupt pending

Switched mode (SWA bit =0):

0: No R+ action

1: The hardware will increment the ST[3:0] bits

when the next commutation occurs and shift all

timer registers right.

Speed Sensor mode (SWA bit =x, TES[1:0] bits

=01, 10, 11):

0: No R+ interrupt pending

1: R+ Interrupt pending

Bit 5 = RMI: Ratio Decrement interrupt flag.

Autoswitched mode (SWA bit =1):

0: No R- interrupt pending

1: R- Interrupt pending

Switched mode (SWA bit =0):

0: No R- action

1: The hardware will decrement the ST[3:0] bits

when the next commutation occurs and shift all

timer registers left.

Speed Sensor mode (SWA bit =x, TES[1:0] bits

=01, 10, 11):

0: No R- interrupt pending

1: R- Interrupt pending

Bit 4 = CLI: Current Limitation interrupt flag.

0: No Current Limitation interrupt pending

1: Current Limitation interrupt pending

Bit 3 = EI: Emergency stop Interrupt flag.

0: No Emergency stop interrupt pending

1: Emergency stop interrupt pending

Bit 2 = ZI: BEMF Zero-crossing interrupt flag.

0: No BEMF Zero-crossing Interrupt pending

1: BEMF Zero-crossing Interrupt pending

Bit 1 = DI: End of Demagnetization interrupt flag.

0: No End of Demagnetization interrupt pending

1: End of Demagnetization interrupt pending

Bit 0 = CI: Commutation / Capture interrupt flag

0: No Commutation / Capture Interrupt pending

1: Commutation / Capture Interrupt pending

Note 1: Loading value FFh in the MISR register

will reset the PWM generator counter and transfer

the compare preload registers in the active regis-

ters by generating a U event (PUI bit set to 1). Re-

fer to “Timer Re-synchronisation” on page 205.

Note 2: When several MTC interrupts are enabled

at the same time the BRES instruction must not be

used to avoid unwanted clearing of status flags: if

a second interrupt occurs while BRES is executed

(which performs a read-modify-write sequence) to

clear the flag of a first interrupt, the flag of the sec-

ond interrupt may also be cleared and the corre-

sponding interrupt routine will not be serviced. It is

thus recommended to use a load instruction to

clear the flag, with a value equal to the logical

complement of the bit. For instance, to clear the

PUI flag:

ld MISR, # 0x7F.

Note 3: In Autoswitched mode (SWA=1 in the

MRCA register): As all bits in the MISR register are

status flags, they are set by internal hardware sig-

nals and must be cleared by software. Any attempt

to write them to 1 will have no effect (they will be

read as 0) without interrupt generation.

In Switched mode (SWA=0 in the MRCA regis-

ter):

To avoid any losing any interrupts when modifying

the RMI and RPI bits the following instruction se-

quence is recommended:

ld MISR, # 0x9F ; reset both RMI & RPI bits

ld MISR, # 0xBF ; set RMI bit

ld MISR, # 0xDF ; set RPI bit

PUI

RPI

RMI

CLI

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