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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STM32F745VG 데이터시트(PDF) 150 Page - STMicroelectronics |
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STM32F745VG 데이터시트(HTML) 150 Page - STMicroelectronics |
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150 / 227 page  Electrical characteristics STM32F745xx STM32F746xx 150/227 DocID027590 Rev 4 General PCB design guidelines Power supply decoupling should be performed as shown in Figure 43 or Figure 44, depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be ceramic (good quality). They should be placed them as close as possible to the chip. Figure 43. Power supply and reference decoupling (VREF+ not connected to VDDA) 1. VREF+ input is available on all the packages except TFBGA100 whereas the VREF– is available only on UFBGA176 and TFBGA216. When VREF- is not available, it is internally connected to VDDA and VSSA. Figure 44. Power supply and reference decoupling (VREF+ connected to VDDA) 1. VREF+ input is available on all the packages except TFBGA100, whereas the VREF– is available only on UFBGA176 and TFBGA216. When VREF- is not available, it is internally connected to VDDA and VSSA. |
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